Packaging technology for semiconductor manufacturing

Electronic packaging is an indispensable process after the production of integrated circuit chips is completed, and it is a device-to-system bridge. Packaging this production process has a great impact on the quality and competitiveness of microelectronic products. According to the current internationally popular opinion, in the overall cost of microelectronic devices, design accounts for one-third, chip production accounts for one-third, and packaging and testing account for one-third. There is one in the world.

The development of packaging research is so rapid on a global scale, and the challenges and opportunities it faces have never been encountered since the advent of electronic products; the wide range of issues involved in packaging is also rare in many other fields. It is a comprehensive and highly advanced new high-tech discipline from materials to processes, from inorganic to polymers, from large-scale production equipment to computational mechanics.

What is a package?

The original definition of the package is to protect the circuit chip from the surrounding environment (including physical and chemical effects). The chip package is a process in which a chip and other elements are arranged, bonded, fixed and connected on a frame or a substrate by using (membrane technology) and (microfabrication technology), and the terminal is led out and potted and fixed by a plastic insulating medium to form an integral structure.

Electronic packaging engineering: The components such as the substrate, the chip package and the discrete components are connected and assembled according to the requirements of the electronic whole machine, and the electrical and physical properties are realized, and the whole device or device having the whole machine or system form is transformed.

The integrated circuit package protects the chip from or is less affected by the external environment and provides a good working condition for the integrated circuit to have stable and normal functions. Chip package can achieve power distribution; signal distribution; heat dissipation channel; mechanical support;

The level of packaging technology:

The first level, also known as chip-level packaging, refers to the process of connecting and fixing the circuit between the integrated circuit chip and the package substrate or the lead frame to make it easy to pick up and place, and The next level of assembly is the module component that is connected.

The second level is the process of forming a number of first-level packages and other electronic components into an electronic card.

At the third level, a circuit card composed of a plurality of packages completed in the second level is combined into a process of making it a component or subsystem on a main circuit board.

The fourth level is the process of assembling several subsystems into a complete electronic product. They are in turn a chip interconnect (zero-level package), a first-level package (multi-chip component), a second-level package (PWB or card) three-level package (motherboard).

Package classification

According to the number of integrated circuit chips in the package, the chip package can be divided into two types: single-chip package and multi-chip package; according to the material of the seal, it can be divided into polymer materials and ceramics; according to the device and circuit Board interconnection mode, the package can be divided into two types: pin insertion type and surface mount type; according to the pin distribution form, the package components have single-sided pins, bilateral pins, four-sided pins, and bottom pins four. Kind.

Common single-sided pins are available in single-row and cross-pin packages; bilateral pin components are available in a dual-package miniaturized package; four-sided pins are available in a four-sided flat package; and the bottom pins are metal can and dot array Package.

Encapsulated noun explanation

SIP: Single-row package SQP: Miniaturized package MCP: Metal package

DIP: Dual In-Line Package CSP: Chip Size Package QFP: Quad Flat Package

PGA: dot matrix package BGA: ball grid array package LCCC: leadless ceramic chip carrier

The development stage of packaging technology

There are different standards for the division of chip packaging technology in the semiconductor industry. At present, the relatively common standard in China is to divide the connection between packaged chips and substrates. In general, the development of integrated circuit package technology can be divided into four stages:

The first stage: before the 1980s (the original era of jacks).

The main technology of the package is pin-inserted (PTH), which is characterized by the jacks mounted on the PCB. The main forms are SIP, DIP, PGA. Their shortcomings are that density and frequency are difficult to improve, and it is difficult to meet the requirements of efficient automated production. .

The second stage: the mid-1980s (surface mount era).

The main feature of the surface mount package is that the lead is replaced by a pin. The lead is wing-shaped or butyl-shaped. The two or four sides are led out with a pitch of 1.27 to 0.4 mm. It is suitable for 3-300 leads. The surface mount technology changes the traditional PTH. In the form of a plug-in, the integrated circuit is mounted on the PCB through tiny leads. The main forms are SOP (small outline package), PLCC (plastic leaded chip carrier), PQFP (plastic four-sided lead flat package), J-type lead QFJ and SOJ, LCCC (leadless ceramic chip carrier) and the like. Their main advantages are thin and short leads, small pitch, increased packing density, improved electrical performance, small size and light weight, and easy automation. Their shortcomings are that it is difficult to meet the needs of ASIC and microprocessor development in terms of package density, I/O count and circuit frequency.

The third stage: a second leap in the 1990s, entered the era of area array packaging.

The main package forms at this stage are solder ball array package (BGA), chip size package (CSP), leadless quad flat package (PQFN), multi-chip module (MCM). The BGA technology makes the pins occupying a large volume and weight in the package replaced by solder balls, and the connection distance between the chip and the system is greatly shortened. The successful development of the BGA technology makes the package that has been lagging behind the development of the chip finally catch up with the chip. The pace of development. CSP technology solves the long-standing fundamental contradiction of small chip and large package, which has triggered a revolution in integrated circuit packaging technology.

The fourth stage: entering the 21st century, ushered in the era of micro-electronic packaging technology stacked package, it has revolutionized the concept of packaging, from the original concept of package components into a packaging system.

At present, the mainstream of global semiconductor packaging is in the mature stage of the third stage, and major packaging technologies such as PQFN and BGA are mass-produced, and some products have begun to develop in the fourth stage. Microelectromechanical systems (MEMS) chips are stacked in a three-dimensional package.

Packaging process

1. The packaging process can generally be divided into two parts. The process steps before the plastic packaging become the front stage operation, and the process steps after the molding become the latter stage operation.

2. The basic process flow of chip packaging technology, silicon wafer thinning, silicon chip cutting chip mounting, chip interconnect molding technology, flashing, burr cutting, forming, soldering, etc.

3. The backside thinning technology of silicon wafer mainly includes grinding, grinding, chemical mechanical polishing, dry polishing, electrochemical corrosion, wet etching, plasma enhanced chemical corrosion, atmospheric pressure plasma corrosion, etc.

4. Thinning after dicing: Before the back grinding, the front side of the silicon wafer is cut into a certain depth of the cut, and then the back grinding is performed.

5. Thinning dicing: Before thinning, the cutting is cut mechanically or chemically, and then thinned to a certain thickness by grinding method. ADPE etching technology is used to remove the remaining processing amount to realize the automatic separation of the bare chip.

6. Four ways of chip mounting: eutectic paste method, solder paste method, conductive paste method, and glass glue paste method. Eutectic bonding method: an IC chip is bonded and fixed by a eutectic fusion reaction at 363 degrees using a gold-silicon alloy (generally 69% Au, 31% Si).

7. In order to obtain the method adopted by Zui Jia's eutectic mounting, the back surface of the IC chip is usually first coated with a gold film or the prechip is implanted on the chip carrier of the substrate.

8. Common methods of chip interconnection are wire bonding, which is carried in automatic bonding (TAB) and flip chip bonding.

9. Wire bonding technology, ultrasonic bonding, hot pressing bonding, thermal ultrasonic bonding.

10. TAB's key technologies: 1 chip bump fabrication technology 2TAB carrier tape fabrication technology 3 carrier wire and chip bump inner lead soldering and carrier tape outer wire bonding technology.

11. The manufacturing process of bump chip, the technology of forming bumps: evaporation/sputter coating method, plating bump production method and stencil printing, solder bumping, electroless plating point method, playing convex Point making method, laser method.

12. Plastic packaging molding technology, 1 transfer molding technology, 2 injection molding technology, 3 pre-forming technology, but the most important technology is transfer molding technology. The materials used in transfer technology are generally thermosetting polymers.

13. The thinned chip has the following advantages: 1. The thin chip is more conducive to heat dissipation; 2. The chip package volume is reduced; 3. The mechanical properties are improved, the silicon wafer is thinned, and the flexibility is better, which is caused by external force impact. The smaller the stress is, the thinner the thickness of the wafer is, the shorter the connection between the components is, the lower the on-resistance of the component will be, and the shorter the signal delay time is, thereby achieving higher performance; After the processing amount is reduced and then cut, the amount of dicing processing can be reduced, and the incidence of chip chipping can be reduced.

14. Wave soldering: The wave soldering process consists of soldering, preheating, and passing the PCB through a solder wave. Depending on the combination of surface tension and capillary action, the solder is brought to the PCB and component leads. Form solder joints.

Wave soldering is a molten liquid solder that forms a specific shape of solder wave on the surface of the solder bath by means of a pump. The PCB on which the component is mounted is placed on the transport chain at a certain angle and a certain depth of penetration. The solder joint process is achieved by solder peaks.

Reflow soldering: The surface assembly component is soldered by pre-applying an appropriate amount and appropriate form of solder on the solder joint of the PCB, then attaching the surface mount components, and then re-melting the solder paste previously dispensed onto the printed circuit board pads. A group or point-by-point soldering process that mechanically and electrically connects a terminal or pin to a printed circuit board pad.

15. Wire Bonding (WB): A thin metal wire or metal tape is sequentially placed on the chip and the lead pad or the pad of the package substrate to form a circuit interconnection. Wire bonding technology includes ultrasonic bonding, hot pressing bonding, and thermal ultrasonic bonding.

Tape Automated Bonding (TAB): A technique in which a die pad is bonded to an I/O of an electronic package or a metal wiring pad on a substrate by a lead pattern metal foil.

Flip Chip Bonding (FCB): A method in which the chip face is facing down and the die pad is directly interconnected with the substrate pad.

16. Chip Interconnect: The chip pad is connected to the I/O of the electronic package or the metal pad on the substrate. Only the circuit connection between the chip and the package structure can be used to perform the existing functions.

Advanced Packaging Technology SIP

As the Internet of Things era and global terminal electronics gradually move toward multi-functional integration and low-power design, SiP technology that can integrate multiple bare crystals into a single package is receiving increasing attention. In addition to the expansion of the large-scale production and production capacity of SiP, the foundry and IC substrate manufacturers are also competing to meet this market demand.

SIP definition

According to the definition of the International Semiconductor Route Organization (ITRS): SiP is a single component that realizes certain functions by preferentially assembling a plurality of active electronic components with different functions and optional passive components, and other devices such as MEMS or optical devices. Standard packages form a system or subsystem.

Therefore, from the architectural point of view, SiP integrates multiple functional chips, including functional chips such as processors and memories, into one package to achieve a basic and complete function.

SOC definition

Integrate ICs with different functions into one chip. With this method, not only can the volume be reduced, but also the distance between different ICs can be reduced, and the calculation speed of the chip can be improved. The SoC is called a system-on-chip. It is also called a system-on-a-chip. It means that it is a product. It is an integrated circuit with a dedicated target, which contains the complete system and has the entire contents of the embedded software. At the same time, it is a technology to realize the whole process from determining the system function to the software/hardware division and completing the design.

As the packaging technology continues to evolve and the terminal electronics are trending towards lightness and thinness, the demand for SiP is gradually increasing.

The SiP production line must be composed of ecosystems such as substrates, wafers, modules, packaging, testing, and system integration to be able to develop smoothly. On the contrary, in the absence of a complete ecosystem, it is difficult to promote the realization of SiP technology.

Because SiP technology can self-contain a variety of chips in a single package, it has high integration and miniaturization features, and is suitable for electronic products with small size, multi-function, low power consumption and other characteristics.

In terms of various applications, if the original independent package components are changed to SiP technology integration, the package size can be reduced to save space, and the connection lines between components can be shortened to reduce the resistance and improve the electrical effect. The advantages of a small package instead of a large circuit carrier can still maintain the original function of each chip. Therefore, the high integration and miniaturization features make SiP become the development trend of packaging technology in recent years.

In addition, since SiP completely encapsulates the relevant circuit in a package, it can increase the chemical corrosion resistance and anti-stress capability of the circuit carrier, improve the overall reliability of the product, and improve the life of the product.

Compared to SoCs, SiP does not require new-mode wafer design and verification. Instead, it integrates existing wafers with different functions into packaging technology.

In general, the basic packaging technology commonly used in SiP at this stage, including Package on Package (PoP) technology, which is commonly used in smart shou machines, stacks logic ICs and memory ICs. Embedded embedded in active and passive components on the substrate, as well as multi-chip package (MCP), multi-chip module (MCM), Stacking Die, PiP, TSV 2.5D IC, TSV 3D IC, etc. SiP technology category.

Smart shou machine plays the main force of SiP growth drive

Compared with the personal computer era, the demand for mobile devices is more common for SiP. In the case of a smart shou machine, the Internet function is already basic, so Wi-Fi modules related to wireless networks will use SiP technology for integration.

Based on the security and confidentiality considerations developed by the fingerprint identification function, the related chip package also needs SiP to help integrate and reduce the space, making the fingerprint identification module become a widely used market for SiP; in addition, the pressure touch is also smart shou One of the emerging functions of the machine, the built-in pressure touch module (Force Touch) needs the assistance of SiP technology.

In addition, processor modules that integrate application processors (APs) with memory, and MEMS modules related to sensing are also applications of SiP technology.

Wearable device / IoT-driven SiP demand rises

The development of global terminal electronic products is continually moving towards the trend of light, short, multi-functional, low-power consumption, and the growth potential of SiP is growing. After the launch of wearable products such as Apple Watch in 2015, SiP technology was extended to wearable products.

In addition, under the trend of the Internet of Things, it is inevitable to combine various mobile devices, wearable devices, smart transportation, smart medical care, and smart home networks in tandem. Multi-functional heterogeneous chip integration estimates will have huge demand, low power consumption. It will also be an important trend.

As an important foundation of the information industry, packaging technology plays a big role in products. Specifically, there is a huge packaging market that determines product performance, reliability, longevity, and cost. In a certain sense, the competition of the modern electronic information industry is mainly the competition of the electronic packaging industry, which determines the level of modern industrialization to a certain extent.